The present invention relates to integrated circuit memories, and, more particularly, to a circuit for precisely controlling the duty cycle of a clock signal, which is important for the proper operation of a DDR (“Double Data Rate”) integrated circuit memory. It has become increasingly important in digital circuits that an accurate 50% duty cycle clock be generated since actions are taken on both the rising and falling edges of the clock.
In DDR chips, data is input and output on both the rising and falling edges of the clock. DDR systems rely on data being valid during a certain window for both edges of the system clock. Therefore, losses in the duty cycle between the input and final output clocks can make it difficult (or even impossible) to find an acceptable strobe window for both clock edges. Additionally, as clock frequencies continue to increase, small errors in the speed of transferring logic “ones” versus logic “zeroes” become a larger percentage loss (or gain) of duty cycle.
A simple solution for addressing poor duty cycle involves the adjustment of P-channel to N-channel ratios in a final driver of the output clock signal. This method requires a new set of masks and is thusly highly inefficient and costly. Also, any further variations in the manufacturing process could cause another modification to be made, further increasing cost and delaying progress.
More advanced methods make use of a dual-slope integrator scheme to indicate when a signal has a 50% duty cycle, which is well known in the art. This scheme uses two current sources of equal magnitude, one to charge an integrating capacitor when the signal is high and the other to discharge the capacitor when the signal is low. When the signal has a 50% duty cycle, there will be no net charge transferred to the capacitor during a clock cycle. When the signal has a duty cycle greater than 50%, the voltage on the capacitor will increase. When the duty cycle is less than 50%, the voltage on the capacitor will decrease. The voltage on the capacitor can, in turn, be used to control the duty cycle; i.e., a “control voltage” is generated. In some cases, two control voltages have been generated, one using the clock and one using the complement of the clock. In this case, the two control voltages move in opposite directions as the duty cycle diverges from 50%.
A number of different techniques have been proposed for using the above described control voltage to adjust the duty cycle. It is also well known that using the same technique with current sources that are not equal can be used to generate signals with precise duty cycles other than 50%.
Examples of the above techniques are described, for example, in U.S. Pat. No. 7,015,739, U.S. Pat. No. 6,781,419 B2, and U.S. Pat. No. 6,975,100 B2.
The duty cycle deviation is the result of the rising and falling edges of a 50% duty cycle input signal propagating at different rates though the circuitry intervening between the input and a point at which the propagated signal is used. A common approach used for adjusting the duty cycle is to add voltage-controlled duty cycle correcting circuitry to the intervening path. The added duty cycle adjusting circuit in this approach uses the control voltage to cause the rising and falling edge propagation rates to differ in opposite directions to that of the circuitry between the input and the added duty cycle correction circuitry. Thus the duty cycle is adjusted toward the desired value.
In U.S. Pat. No. 6,781,419 B2, the well known voltage-controlled inverter is used to adjust the output slew rates of the rising and falling edges in opposite directions thus adjusting the duty cycle. A voltage-controlled current regulating P-channel transistor is used to control the inverter output rising edge slew rate. An N-channel voltage-controlled regulating transistor is used to control the inverter output falling edge slew rate. The control voltages used to control the P-channel and N-channel transistors are derived from the voltage generated by a dual-slope integrator as described above rather than using this voltage directly.
Prior art methods use P-channel transistors to control either the rising edge or falling edge slew rate. With power supply voltages continuing to decrease, the P-channel transistors become much less accurate at performing this control function. The method of the present invention seeks to overcome this deficiency by using only N-channel transistors for the control function. Prior art methods also use various translations and/or digitizations of the dual-slope integrator output voltage. The method of the present invention seeks to overcome this deficiency by using the dual-slope integrator output voltage directly.
What is desired, therefore, is a simple duty cycle correction circuit for use in an integrated circuit memory that precisely controls the duty cycle of a clock signal.